The present invention relates to a semiconductor device and a method of forming the same and specifically to a semiconductor device including a Metal-Insulator-Metal (MIM) capacitor and a method of forming the same.
A semiconductor capacitor has been widely used as a data storage of unit cells in a DRAM device, a ferroelectric memory device, etc. because of its characteristic of storing electrons. Conventionally, the capacitor includes upper and lower electrodes and a dielectric layer intervening between the upper and lower electrodes. As a capacity of the capacitor increases, the capacitor stores more electrons.
Electrodes of an MIM capacitor of a semiconductor device are formed of metal. Especially, an MIM capacitor having noble metal electrodes has been proposed to prevent reactions between a dielectric layer and electrodes. As semiconductor devices are more highly integrated, a size of the MIM capacitor decreases. Thus, various methods are developed for increasing capacitance of the capacitor within a limited area. U.S. Pat. No. 5,392,189 discloses one method of increasing an area of a lower electrode formed of platinum (Pt). This will be briefly explained with reference to FIGS. 1 and 2.
FIGS. 1 and 2 are cross-sectional views for showing a method of forming a conventional MIM capacitor.
Referring to FIG. 1, a first insulation layer 2 is formed on a semiconductor substrate 1 and a plug 3 is formed to contact the semiconductor substrate 1 via the lower oxide layer 2. A second insulation layer 4 is formed over an entire surface of the semiconductor substrate 1 and the second insulation layer 4 is patterned to form an opening 5 exposing the plug 3.
A platinum layer 6 is formed over the semiconductor substrate 1 having the opening 5. In this case, the platinum layer 6 does not fill the opening 5 but lies on a bottom surface and a sidewall of the opening 5.
Referring to FIG. 2, the platinum layer 6 is polished using a chemical mechanical polishing process sufficiently to expose a top surface of the second insulation layer 4, thereby forming a lower electrode 6a in the opening 6.
A dielectric layer 7 and an upper electrode 8 are formed on the lower electrode 6a. The lower electrode 6a, the dielectric layer 7 and the upper electrode 8 compose a capacitor. The lower electrode 6a is formed to have a concave shape in the opening 5, such that overlapped area between the lower and lower electrodes 6a and 8 increases. That is, an inner sidewall area of the lower electrode 6a and a bottom area correspond to the overlapped area of the lower and upper electrodes 6a and 8. Therefore, the capacitance of the capacitor per substrate area increases.
In the above method of forming a conventional capacitor, the lower electrode 6a is formed through a chemical mechanical polishing (CMP) process applied to the deposited platinum layer 6. However, it is very difficult to polish noble metal layers including the platinum layer 6 using chemical mechanical polishing because of lack of developed slurries, etc. Therefore, pattern defects may occur in the lower electrode 6a. In addition, residues of the platinum layer 6 may remain atop the second insulation layer 4 to cause a bridge between neighboring lower electrodes 6a. As a result, yield can be largely degraded due to defects of semiconductor device.